 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HT46RU24 a/d type 8-bit otp mcu with uart i 2 c is a trademark of philips semiconductors. rev. 1.00 1 april 23, 2008 general description the HT46RU24 is 8-bit, high performance, risc archi - tecture microcontroller devices specifically designed for a/d applications that interface directly to analog signals, such as those from sensors. the advantages of low power consumption, i/o flexibil - ity, programmable frequency divider, timer functions, oscillator options, multi-channel a/d converter, pulse width modulation function, i 2 c interface, uart bus, halt and wake-up functions, enhance the versatility of these devices to suit a wide range of a/d application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsys - tem controllers, etc. features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v 40 bidirectional i/o lines (max.) 1 interrupt input shared with an i/o line one 8-bit and two 16-bit programmable timer/event counter with overflow interrupt on-chip crystal and rc oscillator watchdog timer 8192 16 program memory 384 8 data memory ram supports pfd for sound generation halt function and wake-up feature reduce power consumption up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v 16-level subroutine nesting 8 channels 12-bit resolution a/d converter 4-channel 8-bit pwm output shared with four i/o lines bit manipulation instruction 16-bit table read instruction 63 powerful instructions all instructions in one or two machine cycles low voltage reset function i 2 c bus (slave mode) uart (universal asynchronous receiver/ transmitter) 28-pin skdip/sop, 48-pin ssop packages technical document tools information faqs application note ha0005e controlling the i^2c bus with the ht48 & ht46 mcu series ha0013e ht48 & ht46 lcm interface design ha0017e controlling the read/write function of the ht24 series eeprom using the ht49 series mcus ha0075e mcu reset and oscillator circuits application note
block diagram HT46RU24 rev. 1.00 2 april 23, 2008 ! " # $ % " & " ' ( ) * + $ , - + $ , ' . ) / - 0 ) ! / 1 ) * * + 2 * 3 ) ) ) / ) + + * $ , ' . $ , - / / 4 5 # - ' ) 0 ( * * ( + 2 6 ' * . 1 ' 7 ' 3 ' " / + ' + 2 / 3 ' 3 + ' ' 2 3 + ' ( + 2 6 ' ( 6 . 2 3 pin assignment pin description pin name i/o options description pa0~pa2 pa3/pfd pa4 pa5/int pa6/sda pa7/scl i/o pull-high wake-up pa3 or pfd i/o or serial bus bidirectional 8-bit input/output port. each bit can be configured as wake-up input by option (bit option). software instructions determine the cmos out- put or schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). the pfd and int are pin-shared with pa3 and pa5, respectively. once the i 2 c bus function is used, the internal regis - ters related to pa6 and pa7 cannot be used. pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/an6 pb7/an7 i/o pull-high bidirectional 8-bits input/output port. software instructions determine the cmos output, schmitt trigger input with or without pull-high resistor (deter - mined by pull-high option: bit option) or a/d input. once a pb line is se - lected as an a/d input (by using software control), the i/o function and pull-high resistor are automatically disabled. pc0/tx pc1/rx pc2~pc7 i/o pull-high bidirectional 8-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without pull-high resistor (deter - mine by pull-high option: bit option). tx and rx are pin-shared with pc0 and pc1, once the uart bus function is used, the internal registers related to pc0 and pc1 cannot be used. soft - ware instructions determine the uart function to be used. pd0/pwm0 pd1/pwm1 pd2/pwm2 pd3/pwm3 pd4~pd7 i/o pull-high pwm bidirectional 8-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without a pull-high resistor (de - termined by pull-high option: bit option). the pwm0/pwm1/pwm2/ pwm3 output function are pin-shared with pd0/pd1/pd2/pd3 (depending on the pwm options). HT46RU24 rev. 1.00 3 april 23, 2008 . 4 . 3 . 7 . 1 . . . 6 . . . + 6 8 6 4 6 3 6 7 6 1 6 . 6 6 6 6 6 + 8 4 3 7 1 6 . 1 7 3 4 8 + 6 . 1 7 3 4 8 + 6 . / 1 ' 1 / . ' . 6 ' * + / 6 ' 6 / ' / ' / + ' + * 6 * * 3 7 1 . * + + + ' ' / 7 ' 7 / 3 ' 3 . 1 ' 7 ' 3 ' " * . * 1 * 7 * 3 6 ' ( 6 ' ( ' ( + ' ( + 3 7 1 . 6 4 3 7 1 . 6 + 8 4 3 7 1 6 . 1 7 3 4 8 + 6 . / 1 ' 1 / . ' . 6 ' * + / 6 ' 6 / ' / ' / + ' + + ' ' / 7 ' 7 / 3 ' 3 . 1 ' 7 ' 3 ' " ' ( ' + ' ( + . 6 pin name i/o options description pf0~pf7 i/o pull-high bidirectional 8-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without pull-high resistor (deter - mine by pull-high option: bit option). tmr0 i timer/event counter 0 schmitt trigger input (without pull-high resistor) tmr1 i timer/event counter 1 schmitt trigger input (without pull-high resistor). tmr2 i timer/event counter 2 schmitt trigger input (without pull-high resistor). res i schmitt trigger reset input, active low vss negative power supply, ground vdd positive power supply osc1 osc2 i o crystal or rc osc1 and osc2 are connected to an rc network or a crystal (by options) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v i dd1 operating current (crystal osc, rc osc) 3v no load, f sys =4mhz adc off, uart off 12ma 5v 2.5 5 ma i dd2 operating current (crystal osc, rc osc) 3v no load, f sys =4mhz, adc off, uart on 1.5 3.0 ma 5v 36ma i dd3 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz, adc off, uart off 48ma i dd4 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz, adc off, uart on 510ma i stb1 standby current (wdt enabled) 3v no load, system halt 5 a 5v 10 a i stb2 standby current (wdt disabled) 3v no load, system halt 1 a 5v 2 a v il1 input low voltage for i/o ports, tmr0, tmr1, tmr2 and int 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr0, tmr1, tmr2 and int 0.7v dd v dd v HT46RU24 rev. 1.00 4 april 23, 2008 symbol parameter test conditions min. typ. max. unit v dd conditions v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr1 low voltage reset 1 configuration option: 2.1v 1.98 2.1 2.22 v v lvr2 low voltage reset 2 configuration option: 3.15v 2.98 3.15 3.32 v v lvr3 low voltage reset 3 configuration option: 4.2v 3.98 4.2 4.42 v i ol i/o port sink current 3v v ol =0.1v dd 48 ma 5v 10 20 ma i oh i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 10 ma r ph pull-high resistance 3v 20 60 100 k 5v 10 30 50 k i adc additional power consumption if a/d converter is used 3v t ad =1 s 0.5 1 ma 5v 1.5 3 ma dnl adc differential non-linear 5v t ad =1 s 2 lsb inl adc integral non-linear 5v t ad =1 s 2.5 4 lsb resolu resolution 12 bits a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f timer timer i/p frequency (tmr0/tmr1/tmr2) 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 *t sys t int interrupt pulse width 1 s t ad a/d clock period 1 s t adc a/d conversion time 80 t ad t adcs a/d sampling time 32 t ad t iic i 2 c bus clock period connect to external pull-high resistor 2k 64 *t sys note: *t sys =1/f sys HT46RU24 rev. 1.00 5 april 23, 2008 HT46RU24 rev. 1.00 6 april 23, 2008 functional description execution flow the system clock is derived from either a crystal or an rc oscillator. it is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and ex - ecution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. the pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. if an instruction changes the value of the program counter, two cycles are required to com - plete the instruction. program counter pc the program counter (pc) is 13 bits wide and it controls the sequence in which the instructions stored in the pro - gram rom are executed. the contents of the pc can specify a maximum of 8192 addresses. after accessing a program memory word to fetch an instruction code, the value of the pc is incremented by 1. the pc then points to the memory word containing the next instruc - tion code. when executing a jump instruction, condi - tional skip execution, loading a pcl register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the pc manipulates the program transfer by loading the ad - dress corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; oth - erwise proceed to the next instruction. the lower byte of the pc (pcl) is a readable and writeable register (06h). moving data into the pcl per - forms a short jump. the destination is within 256 loca - tions. when a control transfer takes place, an additional dummy cycle is required. 6 . 6 . 6 . * # ) ) 9 : ; ) ) 9 5 : * # ) ) 9 < : ; ) ) 9 : * # ) ) 9 < : ; ) ) 9 < : < < ) - = ) 9 ) - : execution flow mode program counter *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000000 external interrupt or a/d converter interrupt 0000000000100 timer/event counter 0 overflow 0000000001000 timer/event counter 1 overflow 0000000001100 uart interrupt 0000000010000 i 2 c bus interrupt 0000000010100 timer/event counter 2 overflow 0000000011000 skip program counter + 2 loading pcl *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *12~*0: program counter bits s12~s0: stack register bits #12~#0: instruction code bits @7~@0: pcl bits HT46RU24 rev. 1.00 7 april 23, 2008 program memory eprom the program memory (eprom) is used to store the pro - gram instructions which are to be executed. it also con - tains data, table, and interrupt entries, and is organized into 8192 16 bits which are addressed by the program counter and table pointer. certain locations in the rom are reserved for special usage: location 000h location 000h is reserved for program initialization. after chip reset, the program always begins execution at this location. location 004h location 004h is reserved for the external interrupt service program or a/d conversion interrupt (deter - mined by option). if the int input pin or a/d conver - sion interrupt is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004h. location 008h location 008h is reserved for the timer/event coun - ter 0 interrupt service program. if a timer interrupt re - sults from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the pro - gram begins execution at location 008h. location 00ch this area is reserved for the timer/event counter 1 in- terrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and if the in- terrupt is enabled and the stack is not full, the program begins execution at location 00ch. location 010h this area is reserved for the uart interrupt service program. if the uart interrupt resulting from trans - mission/reception is completed, and if the interrupt is enable and the stack is not full, the program begins execution at location 010h. location 014h this area is reserved for the i 2 c bus interrupt service program. if the i 2 c bus interrupt resulting from a slave address is match or completed one byte of data trans - fer, and if the interrupt is enable and the stack is not full, the program begins execution at location 014h. location 018h this area is reserved for the timer/event counter 2 in - terrupt service program. if a timer interrupt results from a timer/event counter 2 overflow, and if the in - terrupt is enabled and the stack is not full, the program begins execution at location 018h. table location any location in the rom can be used as a look-up ta - ble. the instructions tabrdc [m] (the current page, page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to tblh (table higher-order byte register) (08h). only the destination of the lower-order byte in the table is well-defined; the other bits of the ta - ble word are all transferred to the lower portion of tblh. the tblh is read only, and the table pointer (tblp) is a read/write register (07h), indicating the ta - ble location. before accessing the table, the location should be placed in tblp. all the table related instruc - tions require 2 cycles to complete the operation. these areas may function as a normal rom depend - ing upon the users requirements. ; - ) ) > ? ' ) 0 ) ) / ) 0 ) - @ ) ' 0 ) ) + ) ) > " = 5 ) > - ) 9 1 7 ) a ! : b ) ) ) $ ) + ) ) * ) / ) " = 5 ) > - ) 9 1 7 ) a ! : 7 ) > ' 0 ) ) ) ) > + + + & + + . & + + 4 & + . & * * * & + 4 & + + & + + & * * & + + & * + + & ' 0 ) ) ) ) > program memory instruction table location *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl[m] 11111@7@6@5@4@3@2@1@0 table location note: *12~*0: table location bits p12~p8: current program counter bits @7~@0: table pointer bits HT46RU24 rev. 1.00 8 april 23, 2008 stack register stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 16 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at the state of a subroutine call or an interrupt acknowl - edgment, the contents of the program counter are pushed onto the stack. at the end of the subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt is serviced. this feature prevents stack overflow, allowing the programmer to use the structure more easily. if the stack is full and a call is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return addresses are stored). data memory ram the data memory (ram) is designed with 431 8 bits, and is divided into two functional groups, namely; spe- cial function registers (47 8 bits) and general purpose data memory (bank0: 192 8 bits and bank1:192 8 bits) most of which are readable/writeable, although some are read only. the unused space before 40h is reserved for future ex- panded usage and reading these locations will get 00h . the space before 40h is overlapping in each bank. the general purpose data memory, addressed from 40h to ffh (bank0: bp=00h or bank1: bp=01h), is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0;01h/mp1;03h). the space before 40h is overlapping in each bank. indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] accesses the ram pointed to by mp0 (01h) and mp1(03h) respectively. reading lo - cation 00h or 02h indirectly returns the result 00h. while, writing it indirectly leads to no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers used to access the ram by combining corresponding indirect addressing registers. - ) ) ! ) ! ! ) ) + + ! ) ! ! ) ) / " / " / " & + + & + " + & " / / ( + ( ( ( 6 & & & & " & * * ' / % + + & + & + & + 6 & + . & + 1 & + 7 & + 3 & + 4 & + 8 & + & + / & + & + & + & + * & + & & & 6 & . & 1 & 7 & 3 & 4 & 8 & & / & & & & * & + & & & 6 & . & 1 & 7 & 3 & 4 & 8 & & / & & & & * & 6 + & 6 & 6 & 6 6 & 6 . & / = ) * * & . + & b ) ! ! ) ) c + + c 6 * & 6 1 & % - ) ) 9 8 ) / ; ) / = : / = ) + ram mapping HT46RU24 rev. 1.00 9 april 23, 2008 accumulator acc the accumulator is closely related to alu operations. it is also mapped to location 05h of the ram and capable of operating with immediate data. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operations. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register status the status register (0ah) is 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pdf), and a watchdog time-out flag (to). it also records the status in - formation and controls the operation sequence. except for the to and pdf flags, bits in the status register can be altered by instructions similar to other registers. data written into the status register does not alter the to or pdf flags. operations related to the status register, how- ever, may yield different results from those intended. the to and pdf flags can only be changed by a watchdog timer overflow, chip power-up, or clearing the watchdog timer and executing the halt instruction. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. interrupts the device provides an external interrupt or a/d conver - sion interrupt (by option), three internal timer/event counter interrupt, uart interrupt and the i 2 c bus inter - rupts. the interrupt control register 0 (intc0;0bh) and interrupt control register 1 (intc1;1eh) contains the in - terrupt control bits to set the enable/disable and the in - terrupt request flags. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter - rupt requires servicing within the service routine, the emi bit and the corresponding bit of intc0 and intc1 may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is dec - remented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro- gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. bit no. label function 0 c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1 ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3 ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5 to to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register HT46RU24 rev. 1.00 10 april 23, 2008 the trigger source of interrupt vector 04h could be an external interrupt or an end of a/d conversion, which is determined by a configuration option. if interrupt trigger source is from a/d (not from int pin), the option of trig - ger edge (int ) doesn t work and interrupt occurs only when a/d conversion is completed when eadi and emi are enabled. external interrupts are triggered by a high to low transi - tion of int and the related interrupt request flag (eif; bit 4 of intc0) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (eif) and emi bits will be cleared to disable other interrupts. the a/d converter interrupt is initialized by setting the a/d converter request flag (adf; bit 4 of intc0), caused by an end of a/d conversion. when the interrupt is enabled, the stack is not full and the adf is set, a sub - routine call to location 04h will occur. the related inter - rupt request flag (adf) will be reset and the emi bit cleared to disable further interrupts. the internal timer/event counter 0 interrupt is initial - ized by setting the timer/event counter 0 interrupt re - quest flag (t0f; bit 5 of intc0), which is normally caused by a timer overflow. after the interrupt is en - abled, and the stack is not full, and the t0f bit is set, a subroutine call to location 08h occurs. the related inter - rupt request flag (t0f) is reset, and the emi bit is cleared to disable further maskable interrupts. the timer/event counter 1 and timer/event counter 2 operates in the same manner, the timer/event counter 1 related interrupt request flag is t1f, bit 6 of the intc0 register, and its subroutine call location is 0ch. the timer/event counter 2 related interrupt request flag is t2f, bit 6 of the intc1 register, and its subroutine call location is 018h. the related interrupt request flags, t1f and t2f, will be reset and the emi bit cleared to dis - able further interrupts. the uart bus interrupt is initialized by setting the uart bus interrupt request flag, urf; bit 4 of the intc1 register, caused by transmit data register empty (txif), received data available(rxif), transmission idle (tidle), over run error (oerr) or address detected. when the interrupt is enabled, the stack is not full and the txif, rxif, tidle, oerr bit is set or an address is detected, a subroutine call to location 010h will occur. the related interrupt request flag, urf, will be reset and the emi bit cleared to disable further interrupts. bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei or eadi controls the external interrupt (1= enabled; 0= disabled) or controls the a/d conversion interrupt (1= enabled; 0= disabled) 2 et0i controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) 3 et1i controls the timer/event counter 1 interrupt (1= enabled; 0= disabled) 4 eif or adf external interrupt request flag or a/d conversion interrupt request flags. (1= active; 0= inactive) 5 t0f internal timer/event counter 0 request flag (1= active; 0= inactive) 6 t1f internal timer/event counter 1 request flag (1= active; 0= inactive) 7 for test mode used only. must be written as 0 ; otherwise may result in unpredictable operation. intc0 (0bh) register bit no. label function 0 euri control the uart bus interrupt (1= enabled; 0=disabled) 1 ehi control the i 2 c bus interrupt (1= enabled; 0= disabled) 2 et2i controls the timer/event counter 2 interrupt (1= enabled; 0= disabled) 3 unused bit, read as 0 4 urf uart bus interrupt request flag (1= active; 0= inactive) 5hifi 2 c bus interrupt request flag (1= active; 0= inactive) 6 t2f internal timer/event counter 2 request flag (1= active; 0= inactive) 7 unused bit, read as 0 intc1 (1eh) register HT46RU24 rev. 1.00 11 april 23, 2008 the i 2 c bus interrupt is initialized by setting the i 2 c bus in - terrupt request flag ( hif; bit 5 of intc1), caused by a slave address match (h aas= 1 ) or one byte of data transfer is completed. when the interrupt is enabled, the stack is not full and the hif bit is set, a subroutine call to location 14h will occur. the related interrupt request flag (hif) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to en - able an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt or a/d conversion 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch uart bus interrupt 4 10h i 2 c bus interrupt 5 14h timer/event counter 2 overflow 6 18h the timer/event counter 0/1/2 interrupt request flag (t0f, t1f, t2f), external interrupt request flag (eif), a/d converter request flag (adf), the i 2 c bus interrupt request flag (hif), uart bus interrupt request flag (urf), enable timer/event counter bit (et0i, et1i, et2i), enable external interrupt bit (eei), enable a/d converter interrupt bit (eadi), enable i 2 c bus interrupt bit (ehi), enable uart interrupt bit (euri) and enable master interrupt bit (emi) constitute an interrupt control register 0 (intc0) and an interrupt control register 1 (intc1) which are located at 0bh and 1eh in the data memory. emi, eei, et0i, et1i, et2i, eadi, ehi, euri are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags (t0f, t1f, t2f, eif, adf, hif, urf) are set, they will remain in the intc0 and intc1 register until the interrupts are ser - viced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. inter - rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con - trolled, the original control sequence will be damaged once the call operates in the interrupt subroutine. oscillator configuration there are two oscillator circuits in the mi crocontroller. both are designed for system clocks, namely the rc os - cillator and the crystal oscillator, which are determined by the option. no matter what oscillator type is selected, the signal provides the system clock. the halt mode stops the system oscillator and ignores an external sig - nal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vss is required and the resistance must range from 24k to 1m . the system clock, divided by 4, is available on osc2 with pull-high resistor, which can be used to synchronize external logic. the rc os - cillator provides the most cost effective solution. how - ever, the frequency of oscillation may vary with vdd, temperatures and the chip itself due to process varia- tions. it is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. instead of a crystal, a resona- tor can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required (if the oscillating fre - quency is less than 1mhz). the wdt oscillator is a free running on-chip rc oscillator, and no external components are required. even if the sys - tem enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approximately 65 s at 5v. the wdt oscillator can be dis - abled by option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys - tem clock divided by 4) decided by options. this timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable re - sults. the watchdog timer can be disabled by a option. if the watchdog timer is disabled, all the executions re - lated to the wdt result in no operation. once an internal wdt oscillator (rc oscillator with pe - riod 65 s at 5v normally) is selected, it is divided by - ) - - ) - - $ , ' . . 3 + * system oscillator HT46RU24 rev. 1.00 12 april 23, 2008 2 12 ~2 15 (by option to get the wdt time-out period). the wdt time-out minimum period is 300ms~600ms. this time-out period may vary with temperature, vdd and process variations. by selection from the wdt option, longer time-out periods can be realized. if the wdt time-out is selected 2 15 , the maximum time-out period is divided by 2 15 ~2 16 about 2.1s~4.3s. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. the wdt overflow under normal operation will initialize chip reset and set the status bit to. whereas in the halt mode, the overflow will initialize a warm reset only the program counter and stack pointer are reset to zero. to clear the contents of wdt, three methods are adopted; external reset (a low level to res ), software in- structions, or a halt instruction. the software instruc- tions include clr wdt and the other set clr wdt1 and clr wdt2. of these two types of instruction, only one can be active depending on the option clr wdt times selection option .ifthe clr wdt is selected (i.e. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case clr wdt1 and clr wdt2 are chosen (i.e. clrwdt times equal two), these two instructions must be exe - cuted to clear the wdt; otherwise, the wdt may reset the chip because of time-out. if the wdt time-out period is selected f s /2 12 (option), the wdt time-out period ranges from f s /2 12 ~f s /2 13 , since the clr wdt or clr wdt1 and clr wdt2 instructions only clear the last two stages of the wdt. power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator turned off but the wdt oscillator keeps running (if the wdt oscillator or the real time clock is selected). the contents of the on-chip ram and registers remain unchanged the wdt will be cleared and start recounting (if the wdt clock source is from the wdt oscillator or the real time clock) all of the i/o ports maintain their original status the pdf flag is set and the to flag is cleared the system quits the halt mode by an external reset, an interrupt, an external falling edge signal on port a or a wdt overflow. an external reset causes a device initial - ization and the wdt overflow performs a warm reset . after examining the to and pdf flags, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or by executing the clr wdt in - struction and is set when executing the halt instruc - tion. on the other hand, the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp; and leaves the others in their original status. the port a wake-up and interrupt methods can be con- sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by the option. awakening from an i/o port stimu- lus, the program will resume execution of the next in - struction. if it is awakening from an interrupt, two sequences may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the pro - gram will resume execution at the next instruction. but if the interrupt is enabled and the stack is not full, the regu - lar interrupt response takes place. when an interrupt re - quest flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be dis - abled. if wake-up event occurs, it takes 1024 f sys (sys - tem clock period) to resume normal operation. in other words, a dummy period is inserted after wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. however, if the wake-up results in the next instruction execution, this will be executed per - formed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. $ ' 4 ) - = ' . 0 ! ( ) - = ) = - ( $ ( ) - 5 ) ) ) ' $ ) 2 ) ) ) ' $ ) ) ' $ ) 2 ) ) ) ' $ ) ) ) ' $ ) 2 ) ) ) ' $ ) ) ) ' $ ) 2 ) ) ) ' $ ) 1 7 . 1 6 . 6 watchdog timer HT46RU24 rev. 1.00 13 april 23, 2008 reset there are three ways in which a reset may occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and stack pointer, leaves the other circuits at their original state. some reg - isters remain unaffected during any other reset condi - tions. most registers are reset to the initial condition when the reset conditions are met. examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 00res reset during power-up uures reset during normal operation 01res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys- tem awakes from the halt state or during power up. awaking from the halt state or system power up an sst delay is added. an extra sst delay is added during power up period, and any wake-up from halt may en- able only the sst delay. the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler, divider cleared wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack timer/event counter three timer/event counters (tmr0,tmr1, tmr2) are implemented in the microcontroller. the timer/event counter 0 contains an 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. an internal clock source comes from f sys . the timer/event counter 1 con- tains an 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. an internal clock source comes from f sys /4. the timer/event counter 2 contains an 8-bit pro - grammable count-up counter and the clock may come from an external source or an internal clock source. an internal clock source comes from f sys . the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. there are eight registers related to the timer/event counter 0; tmr0h (0ch), tmr0l (0dh), tmr0c (0eh), the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h) and the timer/event counter 2; tmr2 (2dh), tmr2c (2eh). writing tmr0l (tmr1l) will only put the written data to an internal lower-order byte buffer (8-bit) and writing tmr0h (tmr1h) will transfer the specified data and the con - tents of the lower-order byte buffer to tmr0h (tmr1h) and tmr0l (tmr1l) registers, respectively. the timer/event counter 1/0 preload register is changed by each writing tmr0h (tmr1h) operations. reading tmr0h (tmr1h) will latch the contents of tmr0h (tmr1h) and tmr0l (tmr1l) counters to the destina - ( ) ( & " - ! a 5 ) + 5 > ) - ( ; - 5 reset configuration < ) 5 # ) ) reset timing chart + + = + = + d + * + + = + d * + d * reset circuit note: most applications can use the basic reset cir - cuit as shown, however for applications with extensive noise, it is recommended to use the hi-noise reset circuit. HT46RU24 rev. 1.00 14 april 23, 2008 the registers states are summarized in the following table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 000h 000h 000h 000h 000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pwm0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu hadr xxxx xxx- xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu- hcr 0--0 0--- 0--0 0--- 0--0 0--- 0--0 0--- u--u u--- hsr 100- -0-1 100- -0-1 100- -0-1 100- -0-1 uuuu uuuu hdr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrl xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrh xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu acsr 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu pf 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu tmr2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu HT46RU24 rev. 1.00 15 april 23, 2008 + + + + + + + + + - ) ( ! # ! ) - 4 5 ) - 4 5 ) $ , $ + 2 + + 9 7 < : ) ) 9 3 < : ( ) + ' ' ' 6 ) 7 5 / - ! ) ) / - ! 0 $ - a ) ) " a ) / / $ $ & # ) / " a ) / 7 5 / ) ' 0 ) * + timer/event counter 0 + + - ) ( ! # ! ) - $ , ' . $ 7 5 / - ! ) ) / - ! 0 $ - a ) ) " a ) / / $ $ & # ) / " a ) / 7 5 / ) ' 0 ) * timer/event counter 1 register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* tmr2c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu usr 0000 1011 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu txr/rxr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown + + - ) ( ! # ! ) - 4 5 ) - 4 5 ) $ , $ 2 + 9 ' 2 ' 4 : 4 5 / ) ' 0 ) - ! ) 4 5 / ) ' 0 ) 9 : ) / - ! 0 $ - a ) timer/event counter 2 HT46RU24 rev. 1.00 16 april 23, 2008 tion and the lower-order byte buffer, respectively. read - ing the tmr0l (tmr1l) will read the contents of the lower-order byte buffer. writing tmr2 makes the start - ing value be placed in the timer/event counter 2 preload register and reading tmr2 gets the contents of the timer/event counter 2. the tmr0c (tmr1c, tmr2c) is the timer/event counter 0 (1, 2) control reg - ister, which defines the operating mode, counting en - able or disable and an active edge. the t0m0/t0m1 (tmr0c), t1m0/t1m1 (tmr1c) and t2m0/t2m1 (tmr2c) bits define the operation mode. the event count mode is used to count external events, which means that the clock source is from an external (tmr0, tmr1, tmr2) pin. the timer mode functions as a normal timer with the clock source coming from the in - ternal selected clock source. finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr0, tmr1, tmr2), and the counting is based on the internal se- lected clock source. in the event count or timer mode, the timer/event coun- ter 0 (1) starts counting at the current contents in the timer/event counter and ends at ffffh, the timer/event counter 2 starts counting at the current contents in the timer/event counter and ends at ffh. once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt re - quest flag. in the pulse width measurement mode with the values of the t0on/t1on/t2on and t0e/t1e/t2e bits equal to 1, after the tmr0, tmr1, tmr2 has received a tran - sient from low to high (or high to low if the t0e/t1e/t2e bit is 0 ), it will start counting until the tmr0, tmr1, tmr2 returns to the original level and resets the t0on/t1on/ t2on. the measured result remains in the timer/event counter even if the activated transient occurs again. in other words, only 1-cycle measurement can be made until the t0on/t1on/t2on is set. the cy - cle measurement will re-function as long as it receives further transient pulse. in this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt re - quest, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer on bit should be set to 1. in the pulse width measurement mode, the t0on/t1on/t2on is automatically cleared after the measurement cycle is completed. but in the other two modes, the t0on/t1on/t2on can only be reset by instructions. the overflow of the timer/event counter 0/1/2 is one of the wake-up sources and the overflow of the timer/event counter 0/1 can also be ap - plied to a pfd (programmable frequency divider) out - put at pa3 by options. only one pfd (pfd0 or pfd1) can be applied to pa3 by options. if pa3 is set as pfd output, there are two types of selections; one is pfd0 as the pfd output, the other is pfd1 as the pfd output. pfd0, pfd1 are the timer overflow signals of the timer/event counter 0, timer/event counter 1 respec - tively. no matter what the operation mode is, writing a 0 to et0i or et1i disables the related interrupt service. when the pfd function is selected, executing set [pa].3 instruction to enable pfd output and executing clr [pa].3 instruction to disable pfd output. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also re- loads that data to the timer/event counter. but if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event coun- ter preload register. the timer/event counter still contin- ues its operation until an overflow occurs. when the timer/event counter (reading tmr0/tmr1/ tmr2) is read, the clock is blocked to avoid errors, as this may results in a counting error. blocking of the clock should be taken into account by the programmer. it is strongly recommended to load a desired value into the tmr0/tmr1/tmr2 register first, before turning on the related timer/event counter, for proper operation since the initial value of tmr0/tmr1/tmr2 is unknown. due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then dis - able the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. after this procedure, the timer/event function can be operated normally. the bit0~bit2 of the tmr0c/tmr2c can be used to de - fine the pre-scaling stages of the internal clock sources of timer/event counter. the definitions are as shown. the overflow signal of timer/event counter can be used to generate the pfd signal. the timer prescaler is also used as the pwm counter. ' * * ) ) 6 ) ) " * + * pfd source option HT46RU24 rev. 1.00 17 april 23, 2008 bit no. label function 0 1 2 t0psc0 t0psc1 t0psc2 defines the prescaler stages, t0psc2, t0psc1, t0psc0= 000: f int =f sys 001: f int =f sys /2 010: f int =f sys /4 011: f int =f sys /8 100: f int =f sys /16 101: f int =f sys /32 110: f int =f sys /64 111: f int =f sys /128 3 t0e defines the tmr0 active edge of the timer/event counter: in event counter mode (t0m1,t0m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t0m1,t0m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t0on enable/disable timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 6 7 t0m0 t0m1 defines the operating mode, t0m1, t0m0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh) register bit no. label function 0~2 unused bit, read as 0 3 t1e defines the tmr1 active edge of the timer/event counter: in event counter mode (t1m1,t1m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t1m1,t1m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t1on enable/disable timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 6 7 t1m0 t1m1 defines the operating mode, t1m1, t1m0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr1c (11h) register HT46RU24 rev. 1.00 18 april 23, 2008 bit no. label function 0 1 2 t2psc0 t2psc1 t2psc2 defines the prescaler stages, t2psc2, t2psc1, t2psc0= 000: f int =f sys 001: f int =f sys /2 010: f int =f sys /4 011: f int =f sys /8 100: f int =f sys /16 101: f int =f sys /32 110: f int =f sys /64 111: f int =f sys /128 3 t2e defines the tmr2 active edge of the timer/event counter: in event counter mode (t2m1,t2m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t2m1,t2m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t2on enables/disables the timer counting (0=disable; 1=enable) 5 unused bit, read as 0 6 7 t2m0 t2m1 defines the operating mode, t2m1, t2m0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr2c (2eh) register input/output ports there are 40 bidirectional input/output lines in the microcontroller, labeled as pa, pb, pc, pd and pf, which are mapped to the data memory of [12h], [14h], [16h], [18h] and [28h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the in- puts must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h, [18h] or 28h). for out - put operation, all the data is latched and remains un - changed until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc, pfc) to control the input/output configura - tion. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. to function as an input, the corresponding latch of the control register must write 1 . the input source also de - pends on the control register. if the control register bit is 1 , the input will read the pad state. if the control regis - ter bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify- write instruction. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h, 17h, 19h and 29h. after a chip reset, these input/output lines remain at high levels or floating state (depends on pull-high options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h, 16h 18h or 28h) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. each i/o port has a pull-high option. once the pull-high option is selected, the i/o port has a pull-high resistor, otherwise, there s none. take note that a non-pull-high i/o port operating in input mode will cause a floating state. the pa3 and pa5 are pin-shared with the pfd and int pins respectively. if the pfd option is selected, the out - put signal in output mode of pa3 will be the pfd signal generated by timer/event counter overflow signal. the input mode always remain in its original functions. once the pfd option is selected, the pfd output signal is con - trolled by pa3 data register only. writing 1 to pa3 data register will enable the pfd output function and writing 0 will force the pa3 to remain at 0 . the i/o functions of pa3 are shown below. HT46RU24 rev. 1.00 19 april 23, 2008 i/o mode i/p (normal) o/p (normal) i/p (pfd) o/p (pfd) pa3 logical input logical output logical input pfd (timer on) note: the pfd frequency is the timer/event counter overflow frequency divided by 2. the pb can also be used as a/d converter inputs. the a/d function will be described later. there is a pwm function shared with pd0/pd1/pd2/pd3. if the pwm function is enabled, the pwm0/pwm1/pwm2/pwm3 signal will appear on pd0/pd1/pd2/pd3 (if pd0/pd1/ pd2/pd3 is operating in output mode). the i/o func - tions of pd0/pd1/pd2/pd3 are as shown. i/o mode i/p (normal) o/p (normal) i/p (pwm) o/p (pwm) pd0~ pd3 logical input logical output logical input pwm0~ pwm3 it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. pwm the microcontroller provides 4 channels (6+2)/(7+1) (de - pends on options) bits pwm output shared with pd0/pd1/pd2/pd3. the pwm channels have their data registers denoted as pwm0 (1ah), pwm1 (1bh), pwm2 (1ch) and pwm3 (1dh). the frequency source of the pwm counter comes from f sys . the pwm registers are four 8-bit registers. the waveforms of pwm outputs are as shown. once the pd0/pd1/pd2/pd3 are selected as the pwm outputs and the output function of pd0/pd1/pd2/pd3 are enabled (pdc.0/pdc.1/ pdc.2/pdc.3 = 0 ), writing 1 to pd0/pd1/pd2/pd3 data register will enable the pwm output function and writ - ing 0 will force the pd0/pd1/pd2/pd3 to stay at 0 . ! ) ) e e e - ) / ) / ( ) - ) # ) ! ) - ) ( ) ) ) / ' e ) ) - - 5 # # pc1/rx input/output ports ! ) ) e e e - ) / ) / ( ) - ) # ) ! ) - ) ( ) ) ) / + ' e * ) ) ) f ) - - 5 # # pc0/tx input/output ports HT46RU24 rev. 1.00 20 april 23, 2008 9 * ) ( + 2 ( 6 : ( = 5 ) ) $ ) 1 ) - ) ( = 5 9 ) - : ! ) ) e e e - ) / - - 5 & # ) / ( ) - ) # ) ! ) - ) ( ) ) ) / + 2 6 ' * . 1 ' 7 ' 3 ' " / + ' + 2 / 3 ' 3 2 3 + ' ( + ' ( ' ( 6 ' ( 6 . 2 3 * + 2 * 3 e ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) g 6 ? ) * h ) ) ) ) g + ? ( + h ) g ? ( h ) g ? ( h ) g 6 ? ( 6 h pa, pb, pc2~pc7, pd, pf input/output ports a (6+2) bits mode pwm cycle is divided into four modu - lation cycles (modulation cycle 0~modulation cycle 3). each modulation cycle has 64 pwm input clock period. in a (6+2) bit pwm function, the contents of the pwm register is divided into two groups. group 1 of the pwm register is denoted by dc which is the value of pwm.7~pwm.2. the group 2 is denoted by ac which is the value of pwm.1~pwm.0. in a (6+2) bits mode pwm cycle, the duty cycle of each modulation cycle is shown in the table. parameter ac (0~3) duty cycle modulation cycle i (i=0~3) i h ) i + + g ( h ) i + ( g ( h ) i + ( g ( h ) i + 6 ( ( ) - ) b ) 1 7 ' $ , 1 ' 7 . 7 ' 7 . 7 ' 7 . 7 ' 7 . 1 ' 7 . 1 ' 7 . 1 ' 7 . 1 ' 7 . 1 ' 7 . 1 ' 7 . 1 ' 7 . 7 ' 7 . 7 ' 7 . 1 ' 7 . 1 ' 7 . 7 ' 7 . 1 ' 7 . 7 ' 7 . 7 ' 7 . 7 ' 7 . ! - ) - ) + ( ) ! - ) ! ) b ) 7 . ' $ , ! - ) - ) ! - ) - ) ! - ) - ) 6 ! - ) - ) + (6+2) pwm mode HT46RU24 rev. 1.00 21 april 23, 2008 the modulation frequency, cycle frequency and cycle duty of the pwm output signal are summarized in the following table. pwm modulation frequency pwm cycle frequency pwm cycle duty f sys /64 for (6+2) bits mode f sys /128 for (7+1) bits mode f sys /256 [pwm]/256 a/d converter the 8 channels and 12-bit resolution a/d converter are implemented in this microcontroller. the reference volt- age is vdd. the a/d converter contains 4 special regis- ters which are; adrl (24h), adrh (25h), adcr (26h) and acsr (27h). the adrh and adrl are a/d result register higher-order byte and lower-order byte and are read-only. after the a/d conversion is completed, the adrh and adrl should be read to get the conversion result data. the adcr is an a/d converter control regis - ter, which defines the a/d channel number, analog channel select, start a/d conversion control bit and the end of a/d conversion flag. if the users want to start an a/d conversion, define pb configuration, select the con - verted analog channel, and give start bit a raising edge and falling edge (0 1 0). at the end of a/d con - version, the eocb bit is cleared and an a/d converter interrupt occurs (if the a/d converter interrupt is en - abled). the acsr is a/d clock setting register, which is used to select the a/d clock source. the a/d converter control register is used to control the a/d converter. the bit2~bit0 of the adcr are used to select an analog input channel. there are a total of eight channels to select. the bit5~bit3 of the adcr are used to set pb configurations. pb can be an analog input or as digital i/o line decided by these 3 bits. once a pb line is selected as an analog input, the i/o functions and pull-high resistor of this i/o line are disabled and the a/d converter circuit is power on. the eocb bit (bit6 of the adcr) is end of a/d conversion flag. check this bit to know when a/d conversion is completed. the start bit of the adcr is used to begin the conversion of the a/d converter. giving start bit a rising edge and fall - ing edge means that the a/d conversion has started. in order to ensure the a/d conversion is completed, the start should remain at 0 until the eocb is cleared to 0 (end of a/d conversion). bit 7 of the acsr register is used for test purposes only and must not be used for other purposes by the applica- tion program. bit1 and bit0 of the acsr register are used to select the a/d clock source. when the a/d conversion has completed, the a/d inter- rupt request flag will be set. the eocb bit is set to 1 when the start bit is set from 0 to 1 . important note for a/d initialization: special care must be taken to initialize the a/d con - verter each time the port b a/d channel selection bits are modified, otherwise the eocb flag may be in an un - defined condition. an a/d initialization is implemented by setting the start bit high and then clearing it to zero within 10 instruction cycles of the port b channel selec - tion bits being modified. note that if the port b channel selection bits are all cleared to zero then an a/d initial - ization is not required. acs2 acs1 acs0 analog channel 000 an0 001 an1 010 an2 011 an3 100 an4 101 an5 110 an6 111 an7 analog input channel selection $ , ' ( g ( h ) i + + g ( h ) i + ( g ( h ) i + ( g ( h ) i + 6 ( ( ) ! - ) ! ) b ) 4 ' $ , 1 + ' 4 1 ' 4 1 ' 4 1 ' 4 1 + ' 4 1 + ' 4 1 ' 4 1 ' 4 1 + ' 4 1 ' 4 1 ' 4 1 ' 4 ! - ) - ) + ( ) - ) b ) 1 7 ' $ , ! - ) - ) ! - ) - ) + (7+1) pwm mode HT46RU24 rev. 1.00 22 april 23, 2008 bit no. label function 0 1 2 acs0 acs1 acs2 defines the analog channel select 3 4 5 pcr0 pcr1 pcr2 defines the port b configuration select. if pcr0, pcr1 and pcr2 are all zero, the adc circuit is power off to reduce power consumption 6 eocb indicates end of a/d conversion. (0 = end of a/d conversion) each time bits 3~5 change state the a/d should be initialized by issuing a start signal, other - wise the eocb flag may have an undefined condition. see important note for a/d initialization . 7 start starts the a/d conversion. (0 1 0= start; 0 1= reset a/d converter and set eocb to 1 ) adcr (26h) register pcr2pcr1pcr076543210 0 0 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 0 0 1 pb7 pb6 pb5 pb4 pb3 pb2 pb1 an0 0 1 0 pb7 pb6 pb5 pb4 pb3 pb2 an1 an0 0 1 1 pb7 pb6 pb5 pb4 pb3 an2 an1 an0 1 0 0 pb7 pb6 pb5 pb4 an3 an2 an1 an0 1 0 1 pb7 pb6 pb5 an4 an3 an2 an1 an0 1 1 0 pb7 pb6 an5 an4 an3 an2 an1 an0 1 1 1 an7 an6 an5 an4 an3 an2 an1 an0 port b configuration bit no. label function 0 1 adcs0 adcs1 selects the a/d converter clock source 00= system clock/2 01= system clock/8 10= system clock/32 11= undefined 2~6 unused bit, read as 0 7 test for test mode used only acsr (27h) register register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 adrl d3 d2 d1 d0 adrh d11 d10 d9 d8 d7 d6 d5 d4 note: d0~d11 is a/d conversion result data bit lsb~msb. adrl (24h), adrh (25h) register HT46RU24 rev. 1.00 23 april 23, 2008 the following two programming examples illustrate how to setup and implement an a/d conversion. in the first exam - ple, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using eocb polling method to detect end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock mov a,00100000b ; setup adcr register to configure port pb0~pb3 as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : : ; as the port b channel bits have changed the following start ; signal (0-1-0) must be issued within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adrh ; read conversion result high byte value from the adrh register mov adrh_buffer,a ; save result to user defined memory mov a,adrl ; read conversion result low byte value from the adrl register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next a/d conversion example: using interrupt method to detect end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock mov a,00100000b ; setup adcr register to configure port pb0~pb3 as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : ; as the port b channel bits have changed the following start ; signal (0-1-0) must be issued within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request flag set eadi ; enable adc interrupt set emi ; enable global interrupt : : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defined memory mov a,status mov status_stack,a ; save status to user defined memory : : mov a,adrh ; read conversion result high byte value from the adrh register mov adrh_buffer,a ; save result to user defined register mov a,adrl ; read conversion result low byte value from the adrl register mov adrl_buffer,a ; save result to user defined register clr start set start ; reset a/d clr start ; start a/d : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defined memory mov a,acc_stack ; restore acc from user defined memory reti HT46RU24 rev. 1.00 24 april 23, 2008 low voltage reset lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as changing a battery, the lvr will au - tomatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in their original state to exceed 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip operation at 4mhz system clock. 1 d 1 . d d + d 8 " 1 d 1 1 d 1 6 d 1 d + d 8 " 1 d 1 1 d 1 d d + d 8 " 1 d 1 1 d 1 " + d 8 + ) - j j - ) " ) ) - low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. ' ) 0 ) ' ) 0 ) ' ) 0 ) + + + / + + + / + + / + + / / 2 + 2 + a 5 ! ) $ ) ' 0 b ) $ ) / ) $ b ) - ) - ) # - ' ) - = ) ) > ) $ , ' ? ) $ , ' 4 ) ) $ , ' 6 i 6 i 4 + b ) ) $ ) ' 0 ) ' 0 ' ) - ) ) ) ) + + / + + + / ) $ ) ' 0 ) ' 0 + + + / d ) / ) ) ) ) ' d ) ' ) 0 ) ) a ! ) $ $ ) ) ) ) ) ! ) a ) + / + + / ) $ ) ' 0 ) ' 0 ! k ) ! ) $ ) ' 0 ! ) $ ) ' 0 ) ) ) - ) ! ! ? ) ; ) ) ) - ) - - a ! ' ) - ) ) ) ) ' ) - ) ) ) ) a/d conversion timing HT46RU24 rev. 1.00 25 april 23, 2008 i 2 c bus serial interface i 2 c bus is implemented in the device. the i 2 c bus is a bidirectional two-wire lines. the data line and clock line are implement in sda pin and scl pin. the sda and scl are nmos open drain output pin. they must con - nect a pull-high resistor respectively. using the i 2 c bus, the device has two ways to transfer data. one is in slave transmit mode, the other is in slave receive mode. there are four registers related to i 2 c bus; hadr([20h]), hcr([21h]), hsr([22h]), hdr([23h]). the hadr register is the slave address setting of the device, if the master sends the calling ad - dress which match, it means that this device is selected. the hcr is i 2 c bus control register which defines the device enable or disable the i 2 c bus as a transmitter or as a receiver. the hsr is i 2 c bus status register, it re - sponds with the i 2 c bus status. the hdr is input/output data register, data to transmit or receive must be via the hdr register. the i 2 c bus control register contains three bits. the hen bit defines whether to enable or disable the i 2 c bus. if the data wants to transfer via i 2 c bus, this bit must be set. the htx bit defines whether the i 2 c bus is in transmit or receive mode. if the device is as a trans - mitter, this bit must be set to 1 . the txak defines the transmit acknowledge signal, when the device received 8-bit data, the device sends this bit to i 2 c bus at the 9th clock. if the receiver wants to continue to receive the next data, this bit must be reset to 0 before receiving data. the i 2 c bus status register contains 5 bits. the hcf bit is reset to 0 when one data byte is being transferred. if one data transfer is completed, this bit is set to 1 . the haas bit is set 1 when the address is match, and the i 2 c bus interrupt request flag is set to 1 . if the interrupt is enabled and the stack is not full, a subroutine call to location 10h will occur. writing data to the i 2 c bus con - trol register clears haas bit. if the address is not match, this bit is reset to 0 . the hbb bit is set to respond the i 2 c bus is busy. it mean that a start signal is detected. this bit is reset to 0 when the i 2 c bus is not busy. it means that a stop signal is detected and the i 2 c bus is free. the srw bit defines the read/write command bit, if the calling address is match. when haas is set to 1 , the device check srw bit to determine whether the de - vice is working in transmit or receive mode. when srw bit is set 1 , it means that the master wants to read data from i 2 c bus, the slave device must write data to i 2 c bus, so the slave device is working in transmit mode. when srw is reset to 0 , it means that the master wants to write data to i 2 c bus, the slave device must read data from the bus, so the slave device is working in receive mode. the rxak bit is reset 0 indicates an ac - knowledges signal has been received. in the transmit mode, the transmitter checks rxak bit to know the re - ceiver which wants to receive the next data byte, so the transmitter continue to write data to the i 2 c bus until the rxak bit is set to 1 and the transmitter releases the sda line, so that the master can send the stop signal to release the bus. the hadr bit7-bit1 define the device slave address. at the beginning of transfer, the master must select a de - vice by sending the address of the slave device. the bit 0 is unused and is not defined. if the i 2 c bus receives a start signal, all slave device notice the continuity of the 8-bit data. the front of 7 bits is slave address and the first bit is msb. if the address is match, the haas status bit is set and generate an i 2 c bus interrupt. in the isr, the slave device must check the haas bit to know the i 2 c bus interrupt comes from the slave address that has match or completed one 8-bit data transfer. the last bit of the 8-bit data is read/write command bit, it responds in srw bit. the slave will check the srw bit to know if the master wants to transmit or receive data. the device check srw bit to know it is as a transmitter or receiver. bit7~bit1 bit0 slave address means undefined hadr (20h) register the hdr register is the i 2 c bus input/output data regis - ter. before transmitting data, the hdr must write the data which needs to be transmitted. before receiving data, the device must dummy read data from hdr. transmit or receive data from i 2 c bus must be via the hdr register. at the beginning of the transfer of the i 2 c bus, the de - vice must initial the bus, the following are the notes for initialing the i 2 c bus: HT46RU24 rev. 1.00 26 april 23, 2008 & i l & i ) ) ) ) l ( i ) ) ) ) ) l , , i l , ! ) $ ) & , ) ! $ ) & ( ) ) & ) & ( ) ) & ) ! * ) & " ) & " ) " ) & " ) ) ) ( ) - 0 ) ) ! ! ) ) & ) & ) ) ) ) / i l ) > - > - ) ) ) ) & ( ) $ ) % ) ) " ) & ) - - ) & * ) ) ! ! ) a # ) ) ) ) ) / ) ) % ) ) HT46RU24 rev. 1.00 27 april 23, 2008 + ) ) ) ) ) ) ) + + ) ) ) ) ) ) ) + + + + + + i ) 9 ) > : i - 0 ) ! ! ) 9 3 ) > : i ( ) > ) 9 ) > : i - 0 ) ! 0 ) ! ) = a - ! ) > ) 9 ) > : i ) 9 4 ) > : i ) 9 ) > ) $ ) ? ) ) > ) $ ) 0 ) ) > : i ) 9 ) > : " ( " - 0 ) ! ! i 2 c communication timing diagram note: 1: w rite the i 2 c bus address register (hadr) to define its own slave address. 2: set hen bit of i 2 c bus control register (hcr) bit 0 to enable the i 2 c bus. bit no. label function 0~2 unused bit, read as 0 3 txak enable/disable transmit acknowledge (0= acknowledge; 1= don t acknowledge) 4 htx defines the transmit/receive mode (0= receive mode; 1= transmit) 5~6 unused bit, read as 0 7 hen enable/disable i 2 c bus function (0= disable; 1= enable) hcr (21h) register 3: set ehi bit of the interrupt control register 1 (intc1) bit 1 to enable the i 2 c bus interrupt. bit no. label function 0 rxak rxak is cleared to 0 when the master receives an 8-bit data and acknowledgment at the 9th clock, rxak is set to 1 means not acknowledged. 1 unused bit, read as 0 2srw srw is set to 1 when the master wants to read data from the i 2 c bus, so the slave must transmit data to the master. srw is cleared to 0 when the master wants to write data to the i 2 c bus, so the slave must receive data from the master. 3~4 unused bit, read as 0 5hbb hbb is set to 1 when i 2 c bus is busy and hbb is cleared to 0 means that the i 2 c bus is not busy. 6 haas haas is set to 1 when the calling address has matched, and i 2 c bus interrupt will occur and hcf is set. 7 hcf hcf is cleared to 0 when one data byte is being transferred, hcf is set to 1 indi- cating 8-bit data communication has been finished. hsr (22h) register HT46RU24 rev. 1.00 28 april 23, 2008 start signal the start signal is generated only by the master de - vice. the other device in the bus must detect the start signal to set the i 2 c bus busy bit (hbb). the start sig - nal is sda line from high to low, when scl is high. slave address the master must select a device for transferring the data by sending the slave device address after the start signal. all device in the i 2 c bus will receive the i 2 c bus slave address (7 bits) to compare with its own slave address (7 bits). if the slave address is matched, the slave device will generate an interrupt and save the following bit (8th bit) to srw bit and sends an acknowl - edge bit (low level) to the 9th bit. the slave device also sets the status flag (haas), when the slave address is matched. in interrupt subroutine, check haas bit to know whether the i 2 c bus interrupt comes from a slave address that is matched or a data byte transfer is completed. when the slave address is matched, the device must be in trans- mit mode or receive mode and write data to hdr or dummy read from hdr to release the scl line. srw bit the srw bit means that the master device wants to read from or write to the i 2 c bus. the slave device check this bit to understand itself if it is a transmitter or a receiver. the srw bit is set to 1 means that the mas - ter wants to read data from the i 2 c bus, so the slave de - vice must write data to a bus as a transmitter. the srw is cleared to 0 means that the master wants to write data to the i 2 c bus, so the slave device must read data from the i 2 c bus as a receiver. acknowledge bit one of the slave device generates an acknowledge signal, when the slave address is matched. the master device can check this acknowledge bit to know if the slave device accepts the calling address. if no acknowledge bit, the master must send a stop bit and end the communication. when the i 2 c bus status register bit 6 haas is high, it means the address is matched, so the slave must check srw as a transmitter (set htx) to 1 or as a receiver (clear htx) to 0 . data byte the data is 8 bits and is sent after the slave device has acknowledged the slave address. the first bit is msb and the 8th bit is lsb. the receiver sends the acknowl - edge signal ( 0 ) and continues to receive the next one byte data. if the transmitter checks and there snoac - knowledge signal, then it release the sda line, and the master sends a stop signal to release the i 2 c bus. the data is stored in the hdr register. the transmitter must write data to the hdr before transmitting data and the receiver must read data from the hdr after receiving data. receive acknowledge bit when the receiver wants to continue to receive the next data byte, it generates an acknowledge bit (txak) at the 9th clock. the transmitter checks the acknowledge bit (rxak) to continue to write data to the i 2 c bus or change to receive mode and dummy read the hdr reg - ister to release the sda line and the master sends the stop signal. " ) > ) ) ) > - ) ) ) ) - - a # ) > data timing diagram " start bit " stop bit HT46RU24 rev. 1.00 29 april 23, 2008 uart bus serial interface the HT46RU24 devices contain an integrated full-du - plex asynchronous serial communications uart inter - face that enables communication with external devices that contain a serial interface. the uart function has many features and can transmit and receive data seri - ally by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. the uart function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. uart features the integrated uart function contains the following features: full-duplex, asynchronous communication 8 or 9 bits character length even, odd or no parity options one or two stop bits baud rate generator with 8-bit prescaler parity, framing, noise and overrun error detection support for interrupt on address detect (last character bit=1) separately enabled transmitter and receiver 2-byte deep fifo receive data buffer transmit and receive interrupts interrupts can be initialized by the following conditions: transmitter empty transmitter idle receiver full receiver overrun address mode detect uart external pin interfacing to communicate with an external serial interface, the internal uart has two external pins known as tx and rx. the tx pin is the uart transmitter pin, which can be used as a general purpose i/o pin if the pin is not configured as a uart transmitter, which occurs when the txen bit in the ucr2 control register is equal to zero. similarly, the rx pin is the uart receiver pin, which can also be used as a general purpose i/o pin, if the pin is not configured as a receiver, which occurs if the rxen bit in the ucr2 register is equal to zero. along with the uarten bit, the txen and rxen bits, if set, will automatically setup these i/o pins to their re - spective tx output and rx input conditions and dis - able any pull-high resistor option which may exist on the rx pin. uart data transfer scheme the block diagram shows the overall data transfer structure arrangement for the uart. the actual data to be transmitted from the mcu is first transferred to the txr register by the application program. the data will then be transferred to the transmit shift register from where it will be shifted out, lsb first, onto the tx pin at a rate controlled by the baud rate generator. only the txr register is mapped onto the mcu data memory, the transmit shift register is not mapped and is therefore inaccessible to the application pro - gram. data to be received by the uart is accepted on the external rx pin, from where it is shifted in, lsb first, to the receiver shift register at a rate controlled by the baud rate generator. when the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buffered and can be manipulated by the application program. only the rxr register is mapped onto the mcu data mem- ory, the receiver shift register is not mapped and is therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared reg- ister in the data memory. this shared register known as the txr/rxr register is used for both data trans- mission and data reception. uart status and control registers there are five control registers associated with the uart function. the usr, ucr1 and ucr2 registers control the overall function of the uart, while the brg register controls the baud rate. the actual data to be transmitted and received on the serial interface is managed through the txr/rxr data registers. ) ) / " / ) ) # $ ) ) ) / " / 0 ) ) # $ ) ) ) / ! ) % " " / $ $ ) ) / uart data transfer scheme HT46RU24 rev. 1.00 30 april 23, 2008 usr register the usr register is the status register for the uart, which can be read by the program to determine the present status of the uart. all flags within the usr register are read only. further explanation on each of the flags is given below: txif the txif flag is the transmit data register empty flag. when this read only flag is 0 it indicates that the character is not transferred to the transmit shift registers. when the flag is 1 it indicates that the transmit shift register has received a character from the txr data register. the txif flag is cleared by reading the uart status register (usr) with txif set and then writing to the txr data register. note that when the txen bit is set, the txif flag bit will also be set since the transmit buffer is not yet full. tidle the tidle flag is known as the transmission com - plete flag. when this read only flag is 0 it indicates that a transmission is in progress. this flag will be set to 1 when the txif flag is 1 and when there is no transmit data, or break character being trans - mitted. when tidle is 1 the tx pin becomes idle. the tidle flag is cleared by reading the usr regis - ter with tidle set and then writing to the txr regis - ter. the flag is not generated when a data character, or a break is queued and ready to be sent. rxif the rxif flag is the receive register status flag. when this read only flag is 0 it indicates that the rxr read data register is empty. when the flag is 1 it indicates that the rxr read data register con- tains new data. when the contents of the shift regis- ter are transferred to the rxr register, an interrupt is generated if rie=1 in the ucr2 register. if one or more errors are detected in the received word, the appropriate receive-related flags nf, ferr, and/or perr are set within the same clock cycle. the rxif flag is cleared when the usr register is read with rxif set, followed by a read from the rxr reg - ister, and if the rxr register has no data available. ridle the ridle flag is the receiver status flag. when this read only flag is 0 it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. when the flag is 1 it indicates that the receiver is idle. between the com - pletion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart is idle. oerr the oerr flag is the overrun error flag, which indi - cates when the receiver buffer has overflowed. when this read only flag is 0 there is no overrun er - ror. when the flag is 1 an overrun error occurs which will inhibit further transfers to the rxr receive data register. the flag is cleared by a software se - quence, which is a read to the status register usr followed by an access to the rxr data register. ferr the ferr flag is the framing error flag. when this read only flag is 0 it indicates no framing error. when the flag is 1 it indicates that a framing error has been detected for the current character. the flag can also be cleared by a software sequence which will involve a read to the usr status register followed by an access to the rxr data register. nf the nf flag is the noise flag. when this read only flag is 0 it indicates a no noise condition. when the flag is 1 it indicates that the uart has de- tected noise on the receiver input. the nf flag is set during the same cycle as the rxif flag but will not be set in the case of an overrun. the nf flag can be cleared by a software sequence which will involve a read to the usr status register, followed by an ac - cess to the rxr data register. > 3 " * > + * " * ) ! ) ) b ) # ) $ ! ) ) ) # $ ) ) ) ) ) + b ) # ) ) $ ! ) ) ) # $ ) ) ! - b ) ) ) ) + b ) ) ) 0 ) ) ) b ) ) ) # ) 0 - > - ) ! + b ) ) ) ) 0 ) b ) 0 ) ) ! - + b ) ! ) > ) 0 ! 0 ) b ) 0 ) ) ! ! + b ) ) 0 ) ) ! ! * ) ) $ - b ) $ ) ) ! ! + b ) ) $ ) ) $ - b ) ) ! ! + b ) ) ) ! ! ) ) $ - b ) ) ) ! ! + b ) ) ) ) ! ! * HT46RU24 rev. 1.00 31 april 23, 2008 perr the perr flag is the parity error flag. when this read only flag is 0 it indicates that a parity error has not been detected. when the flag is 1 it indi - cates that the parity of the received word is incor - rect. this error flag is applicable only if parity mode (odd or even) is selected. the flag can also be cleared by a software sequence which involves a read to the usr status register, followed by an ac - cess to the rxr data register. ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uart function, such as overall on/off control, parity control, data transfer bit length etc. further explanation on each of the bits is given below: tx8 this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data, known as tx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. rx8 this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data, known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. txbrk the txbrk bit is the transmit break character bit. when this bit is 0 there are no break characters and the tx pin operates normally. when the bit is 1 there are transmit break characters and the transmitter will send logic zeros. when equal to 1 after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. stops this bit determines if one or two stop bits are to be used. when this bit is equal to 1 two stop bits are used, if the bit is equal to 0 then only one stop bit is used. prt this is the parity type selection bit. when this bit is equal to 1 odd parity will be selected, if the bit is equal to 0 then even parity will be selected. pren this is parity enable bit. when this bit is equal to 1 the parity function will be enabled, if the bit is equal to 0 then the parity function will be disabled. bno this bit is used to select the data length format, which can have a choice of either 8-bits or 9-bits. if this bit is equal to 1 then a 9-bit data length will be selected, if the bit is equal to 0 then an 8-bit data length will be selected. if 9-bit data length is se - lected then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data re - spectively. uarten the uarten bit is the uart enable bit. when the bit is 0 the uart will be disabled and the rx and tx pins will function as general purpose i/o pins. when the bit is 1 the uart will be enabled and the tx and rx pins will function as defined by the txen and rxen control bits. when the uart is disabled it will empty the buffer so any character re- maining in the buffer will be discarded. in addition, the baud rate counter value will be reset. when the uart is disabled, all error and status flags will be reset. the txen, rxen, txbrk, rxif, oerr, ferr, perr, and nf bits will be cleared, while the tidle, txif and ridle bits will be set. other con- trol bits in ucr1, ucr2, and brg registers will re- main unaffected. if the uart is active and the uarten bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. when the uart is re-enabled it will restart in the same configuration. > 3 / > + / 4 4 ) ! ) > ) 4 ) 9 a ) - : 0 ) ! ) > ) 4 ) 9 ! ) - : ) > = ) # b ) ) > = ) # + b ) ) > = ) # $ ) # ) > ) $ ) ) > b ) a ) ) > + b ) ) ) > ) ) > b ) ! ! ) ) $ ) ) + b ) 0 ) ) $ ) ) ) > - ) > b ) ) $ ) > - ! + b ) ) $ ) ! > - ! > ) $ ) ! ) $ ) > b ) 8 5 > ) ! ) $ + b ) 4 5 > ) ! ) $ ) > - ) > b ) > - ) ? ) ) f ) ) ) ) ) + b ) ! > - ) ? ) ) f ) ) ) ) ' ) ) HT46RU24 rev. 1.00 32 april 23, 2008 ucr2 register the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functions is to control the basic enable/dis - able operation of the uart transmitter and receiver as well as enabling the various uart interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below: teie this bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 when the transmit - ter empty txif flag is set, due to a transmitter empty condition, the uart interrupt request flag will be set. if this bit is equal to 0 the uart inter - rupt request flag will not be influenced by the condi - tion of the txif flag. tiie this bit enables or disables the transmitter idle in - terrupt. if this bit is equal to 1 when the transmitter idle tidle flag is set, the uart interrupt request flag will be set. if this bit is equal to 0 the uart in - terrupt request flag will not be influenced by the condition of the tidle flag. rie this bit enables or disables the receiver interrupt. if this bit is equal to 1 when the receiver overrun oerr flag or receive data available rxif flag is set, the uart interrupt request flag will be set. if this bit is equal to 0 the uart interrupt will not be influenced by the condition of the oerr or rxif flags. wake this bit enables or disables the receiver wake-up function. if this bit is equal to 1 and if the mcu is in the power down mode, a low going edge on the rx input pin will wake-up the device. if this bit is equal to 0 and if the mcu is in the power down mode, any edge transitions on the rx pin will not wake-up the device. adden the adden bit is the address detect mode bit. when this bit is 1 the address detect mode is en - abled. when this occurs, if the 8th bit, which corre - sponds to rx7 if bno=0, or the 9th bit, which corresponds to rx8 if bno=1, has a value of 1 then the received word will be identified as an ad - dress, rather than data. if the corresponding inter - rupt is enabled, an interrupt request will be generated each time the received word has the ad - dress bit set, which is the 8 or 9 bit depending on the value of bno. if the address bit is 0 an interrupt will not be generated, and the received data will be discarded. brgh the brgh bit selects the high or low speed mode of the baud rate generator. this bit, together with the value placed in the brg register, controls the baud rate of the uart. if this bit is equal to 1 the high speed mode is selected. if the bit is equal to 0 the low speed mode is selected. rxen the rxen bit is the receiver enable bit. when this bit is equal to 0 the receiver will be disabled with any pending data receptions being aborted. in addi- tion the buffer will be reset. in this situation the rx pin can be used as a general purpose i/o pin. if the rxen bit is equal to 1 the receiver will be enabled and if the uarten bit is equal to 1 the rx pin will be controlled by the uart. clearing the rxen bit during a transmission will cause the data reception to be aborted and will reset the receiver. if this oc- curs, the rx pin can be used as a general purpose i/o pin. > 3 ( > + ) ) ) > - b ) * ) ) m ) > - + b ) * ) ) m ) ! > - ) ! - ) ) > - b ) " ) ) m ) > - + b ) " ) ) m ) ! > - 0 ) ) > - b ) * ) ) m ) > - + b ) * ) ) m ) ! > - $ ) # ) ) a = ) ) > - b ) ) a = ) ) > - ) 9 $ - - ) ! : + b ) ) a = ) ) ! > - ! ! ) ! ) ! b ) > - + b ) ! > - & # ) > ! ) ) - ) > b ) # # ) ! + b ) - a ) ! 0 ) > - ) > b ) 0 ) > - + b ) 0 ) ! > - ) > - ) > b ) ) > - + b ) ) ! > - / % & HT46RU24 rev. 1.00 33 april 23, 2008 txen the txen bit is the transmitter enable bit. when this bit is equal to 0 the transmitter will be disabled with any pending transmissions being aborted. in addition the buffer will be reset. in this situation the tx pin can be used as a general purpose i/o pin. if the txen bit is equal to 1 the transmitter will be enabled and if the uarten bit is equal to 1 the tx pin will be controlled by the uart. clearing the txen bit during a transmission will cause the trans - mission to be aborted and will reset the transmitter. if this occurs, the tx pin can be used as a general purpose i/o pin. baud rate generator to setup the speed of the serial data communication, the uart function contains its own dedicated baud rate generator. the baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. the first of these is the value placed in the brg register and the second is the value of the brgh bit within the ucr2 control regis - ter. the brgh bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value in the brg register determines the division factor, n, which is used in the following baud rate calculation formula. note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate f [64 (n+1)] sys f [16 (n+1)] sys by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register, the required baud rate can be setup. note that because the actual baud rate is determined using a discrete value, n, placed in the brg register, there will be an error associated be - tween the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. calculating the register and error values for a clock frequency of 8mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 9600. from the above table the desired baud rate br f [64 (n+1)] sys re-arranging this equation gives n f (brx64) sys 1 giving a value for n 8000000 9600 64 () x 1 12.0208 to obtain the closest value, a decimal value of 12 should be placed into the brg register. this gives an actual or calculated baud rate value of br 8000000 [64(12 +1)] 9615 therefore the error is equal to = 0.16% the following tables show actual values of baud rate and error values for the two values of brgh. baud rate k/bps baud rates for brgh=0 f sys =8mhz f sys =7.159mhz f sys =4mhz f sys =3.579545mhz brg kbaud error brg kbaud error brg kbaud error brg kbaud error 0.3 207 0.300 0.00 185 0.300 0.00 1.2 103 1.202 0.16 92 1.203 0.23 51 1.202 0.16 46 1.19 -0.83 2.4 51 2.404 0.16 46 2.38 -0.83 25 2.404 0.16 22 2.432 1.32 4.8 25 4.807 0.16 22 4.863 1.32 12 4.808 0.16 11 4.661 -2.9 9.6 12 9.615 0.16 11 9.322 -2.9 6 8.929 -6.99 5 9.321 -2.9 19.2 6 17.857 -6.99 5 18.64 -2.9 2 20.83 8.51 2 18.643 -2.9 38.4 2 41.667 8.51 2 37.29 -2.9 1 1 57.6 1 62.5 8.51 1 55.93 -2.9 0 62.5 8.51 0 55.93 -2.9 115.2 0 125 8.51 0 111.86 -2.9 baud rates and error values for brgh 0 HT46RU24 rev. 1.00 34 april 23, 2008 baud rate k/bps baud rates for brgh=1 f sys =8mhz f sys =7.159mhz f sys =4mhz f sys =3.579545mhz brg kbaud error brg kbaud error brg kbaud error brg kbaud error 0.3 1.2 207 1.202 0.16 185 1.203 0.23 2.4 207 2.404 0.16 185 2.405 0.23 103 2.404 0.16 92 2.406 0.23 4.8 103 4.808 0.16 92 4.811 0.23 51 4.808 0.16 46 4.76 -0.83 9.6 51 9.615 0.16 46 9.520 -0.832 25 9.615 0.16 22 9.727 1.32 19.2 25 19.231 0.16 22 19.454 1.32 12 19.231 0.16 11 18.643 -2.9 38.4 12 38.462 0.16 11 37.287 -2.9 6 35.714 -6.99 5 37.286 -2.9 57.6 8 55.556 -3.55 7 55.93 -2.9 3 62.5 8.51 3 55.930 -2.9 115.2 3 125 8.51 3 111.86 -2.9 1 125 8.51 1 111.86 -2.9 250 1 250 0 0 250 0 baud rates and error values for brgh 1 setting up and controlling the uart introduction for data transfer, the uart function utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uart hardware, and can be setup to be even, odd or no parity. for the most common data format, 8 data bits along with no par- ity and one stop bit, denoted as 8, n, 1, is used as the default setting, which is the setting at power-on. the number of data bits and stop bits, along with the parity, are setup by programming the corresponding bno, prt, pren, and stops bits in the ucr1 register. the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate gen - erator, while the data is transmitted and received lsb first. although the uart s transmitter and re - ceiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart the basic on/off function of the internal uart func - tion is controlled using the uarten bit in the ucr1 register. as the uart transmit and receive pins, tx and rx respectively, are pin-shared with normal i/o pins, one of the basic functions of the uarten con - trol bit is to control the uart function of these two pins. if the uarten, txen and rxen bits are set, then these two i/o pins will be setup as a tx output pin and an rx input pin respectively, in effect dis - abling the normal i/o pin function. if no data is being transmitted on the tx pin then it will default to a logic high value. clearing the uarten bit will disable the tx and rx pins and allow these two pins to be used as normal i/o pins. when the uart function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. disabling the uart will also reset the error and sta- tus flags with bits txen, rxen, txbrk, rxif, oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the re- maining control bits in the ucr1, ucr2 and brg registers will remain unaffected. if the uarten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and recep- tions will be immediately suspended and the uart will be reset to a condition as defined above. if the uart is then subsequently re-enabled, it will restart again in the same configuration. data, parity and stop bit selection the format of the data to be transferred, is com - posed of various factors such as data bit length, parity on/off, parity type, address bits and the num - ber of stop bits. these factors are determined by the setup of various bits within the ucr1 register. the bno bit controls the number of data bits which can be set to either 8 or 9, the prt bit controls the choice of odd or even parity, the pren bit controls the parity on/off function and the stops bit decides whether one or two stop bits are to be used. the fol - lowing table shows various formats for data trans - mission. the address bit identifies the frame as an address character. the number of stop bits, which can be either one or two, is independent of the data length. HT46RU24 rev. 1.00 35 april 23, 2008 start bit data bits address bits parity bits stop bit example of 8-bit data formats 18001 17011 171 1 01 example of 9-bit data formats 19001 18011 181 1 01 transmitter receiver data format the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. uart transmitter data word lengths of either 8 or 9 bits, can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register. at the transmitter core lies the transmitter shift register, more commonly known as the tsr, whose data is ob - tained from the transmit data register, which is known as the txr register. the data to be transmitted is loaded into this txr register by the application pro- gram. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been trans- mitted, the tsr can then be loaded with new data from the txr register, if it is available. it should be noted that the tsr register, unlike many other regis- ters, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmis - sion of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator has defined a shift clock source. how - ever, the transmission can also be initiated by first loading data into the txr register, after which the txen bit can be set. when a transmission of data be - gins, the tsr is normally empty, in which case a transfer to the txr register will result in an immediate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will immediately cease and the transmitter will be reset. the tx output pin will then return to having a normal general purpose i/o pin function. transmitting data when the uart is transmitting data, the data is shifted on the tx pin from the shift register, with the least significant bit first. in the transmit mode, the txr register forms a buffer between the internal bus and the transmitter shift register. it should be noted that if 9-bit data format has been selected, then the msb will be taken from the tx8 bit in the ucr1 register. the steps to initiate a data transfer can be summarized as follows: make the correct selection of the bno, prt, pren and stops bits to define the required word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the txen bit to ensure that the tx pin is used as a uart transmitter pin and not as an i/o pin. access the usr register and write the data that is to be transmitted into the txr register. note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be in - hibited from being written to the txr register. clear - ing the txif flag is always achieved using the following software sequence: 1. a usr register access 2. a txr register write execution the read-only txif flag is set by the uart hard- ware and if set indicates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set then the txif flag will gen- erate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr regis- ter, which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register, resulting in the commencement of data transmission, and the txif bit being immedi - ately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. to clear the tidle bit the following software sequence is used: 1. a usr register access 2. a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. ) / / ) + / ) / ) / ) 6 / ) . / ) 1 / ) 7 / ) 3 ) / ; / ) / ! " ) / / ) + / ) / ) / ) 6 / ) . / ) 1 / ) 7 / ) 3 ) / ; / ) / # ! " / ) 4 HT46RU24 rev. 1.00 36 april 23, 2008 transmit break if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13 n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be first set by the application program, then cleared to generate the stop bits. transmitting a break character will not generate a transmit inter - rupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after the ap - plication program has cleared the txbrk bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. uart receiver introduction the uart is capable of receiving word lengths of ei - ther 8 or 9 bits. if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register. at the receiver core lies the receive serial shift register, commonly known as the rsr. the data which is received on the rx external input pin, is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register, if the register is empty. the data which is received on the external rx input pin is sampled three times by a majority de- tect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register, unlike many other registers, is not di - rectly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uart receiver is receiving data, the data is serially shifted in on the external rx input pin, lsb first. in the read mode, the rxr register forms a buffer between the internal bus and the receiver shift register. the rxr register is a two byte deep fifo data buffer, where two bytes can be held in the fifo while a third byte can continue to be received. note that the application program must ensure that the data is read from rxr before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows: make the correct selection of bno, prt, pren and stops bits to define the word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the rxen bit to ensure that the rx pin is used as a uart receiver pin and not as an i/o pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received the following se - quence of events will occur: the rxif bit in the usr register will be set when rxr register has data available, at least one more character can be read. when the contents of the shift register have been transferred to the rxr register, then if the rie bit is set, an interrupt will be generated. if during reception, a frame error, noise error, par - ity error, or an overrun error has been detected, then the error flags can be set. the rxif bit can be cleared using the following software sequence: 1. a usr register access 2. an rxr register read execution receive break any break character received by the uart will be managed as a framing error. the receiver will count and expect a certain number of bit times as speci - fied by the values programmed into the bno and stops bits. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by bno and stops. the rxif bit is set, ferr is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the re- ceiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr flag, the re- ceiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break condition on the line is the next start bit. a break is regarded as a character that contains only zeros with the ferr flag set. the break character will be loaded into the buffer and no further data will be received until stop bits are re - ceived. it should be noted that the ridle read only flag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the following: the framing error flag, ferr, will be set. the receive data register, rxr, will be cleared. the oerr, nf, perr, ridle or rxif flags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the usr register, otherwise known as the ridle flag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle flag will have a high value, which indicates the receiver is in an idle condition. HT46RU24 rev. 1.00 37 april 23, 2008 receiver interrupt the read only receive interrupt flag rxif in the usr register is set by an edge generated by the receiver. an interrupt is generated if rie=1, when a word is transferred from the receive shift register, rsr, to the receive data register, rxr. an overrun error can also generate an interrupt if rie=1. managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error - oerr flag the rxr register is composed of a two byte deep fifo data buffer, where two bytes can be held in the fifo register, while a third byte can continue to be received. before this third byte has been entirely shifted in, the data should be read from the rxr register. if this is not done, the overrun error flag oerr will be consequently indicated. in the event of an overrun error occurring, the fol - lowing will happen: the oerr flag in the usr register will be set. the rxr contents will not be lost. the shift register will be overwritten. an interrupt will be generated if the rie bit is set. the oerr flag can be cleared by an access to the usr register followed by a read to the rxr register. noise error - nf flag over-sampling is used for data recovery to identify valid incoming data and noise. if noise is detected within a frame the following will occur: the read only noise flag, nf, in the usr register will be set on the rising edge of the rxif bit. data will be transferred from the shift register to the rxr register. no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note that the nf flag is reset by a usr register read operation followed by an rxr register read operation. framing error - ferr flag the read only framing error flag, ferr, in the usr register, is set if a zero is detected instead of stop bits. if two stop bits are selected, both stop bits must be high, otherwise the ferr flag will be set. the ferr flag is buffered along with the received data and is cleared on any reset. parity error - perr flag the read only parity error flag, perr, in the usr register, is set if the parity of the received word is in - correct. this error flag is only applicable if the parity is enabled, pren = 1, and if the parity type, odd or even is selected. the read only perr flag is buf - fered along with the received data bytes. it is cleared on any reset. it should be noted that the ferr and perr flags are buffered along with the corresponding word and should be read before reading the data word. uart interrupt scheme the uart internal function possesses its own inter - nal interrupt and independent interrupt vector. several individual uart conditions can generate an internal uart interrupt. these conditions are, a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. when any of these conditions are cre- ated, if the uart interrupt is enabled and the stack is not full, the program will jump to the uart interrupt vector where it can be serviced before returning to the main program. four of these conditions, have a corre- sponding usr register flag, which will generate a uart interrupt if its associated interrupt enable flag in ) ) * - ) * ) ! - * - ) " 0 ) 0 - > - ) * 0 ) 0 * - ) 3 ) $ ) / i + 4 ) $ ) / i + + ) ( = 5 ( + ) ) m ) * - * + ) + + + uart interrupt scheme HT46RU24 rev. 1.00 38 april 23, 2008 the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable bits, while the two receiver interrupt conditions have a shared enable bit. these enable bits can be used to mask out individual uart interrupt sources. the address detect condition, which is also a uart interrupt source, does not have an associated flag, but will generate a uart interrupt when an address detect condition occurs if its function is enabled by setting the adden bit in the ucr2 register. an rx pin wake-up, which is also a uart interrupt source, does not have an associated flag, but will generate a uart interrupt if the microcontroller is woken up by a low go - ing edge on the rx pin, if the wake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a delay of 1024 system clock cycles before the system re - sumes normal operation. note that the usr register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. the flags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart register section. the overall uart interrupt can be disabled or enabled by the euri bit in the intc1 interrupt control register to prevent a uart in - terrupt from occurring. address detect mode setting the address detect mode bit, adden, in the ucr2 register, enables this special mode. if this bit is enabled then an additional qualifier will be placed on the generation of a receiver data available interrupt, which is requested by the rxif flag. if the adden bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the euri and emi interrupt en - able bits must also be enabled for correct interrupt generation. this highest address bit is the 9th bit if bno=1 or the 8th bit if bno=0. if this bit is high, then the received word will be defined as an address rather than data. a data available interrupt will be generated every time the last bit of the received word is set. if the adden bit is not enabled, then a receiver data avail - able interrupt will be generated each time the rxif flag is set, irrespective of the data last bit status. the address detect mode and parity enable are mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the par - ity enable bit to zero. adden bit 9 if bno=1, bit 8 if bno=0 uart interrupt generated 0 0 1 1 0x 1 adden bit function uart operation in power down mode when the mcu is in the power down mode the uart will cease to function. when the device enters the power down mode, all clock sources to the module are shutdown. if the mcu enters the power down mode while a transmission is still in progress, then the transmission will be terminated and the external tx transmit pin will be forced to a logic high level. in a similar way, if the mcu enters the power down mode while receiving data, then the reception of data will likewise be terminated. when the mcu enters the power down mode, note that the usr, ucr1, ucr2, transmit and receive registers, as well as the brg register will not be affected. the uart function contains a receiver rx pin wake-up function, which is enabled or disabled by the wake bit in the ucr2 register. if this bit, along with the uart enable bit, uarten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set before the mcu enters the power down mode, then a falling edge on the rx pin will wake-up the mcu from the power down mode. note that as it takes 1024 system clock cycles after a wake-up, be- fore normal microcontroller operation resumes, any data received during this time on the rx pin will be ig- nored. for a uart wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uart interrupt enable bit, euri must also be set. if these two bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes 1024 sys - tem clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed. HT46RU24 rev. 1.00 39 april 23, 2008 options the following shows kinds of options in the device. all the options must be defined to ensure proper system function. options osc type selection. this option is to decide if an rc or crystal oscillator is chosen as system clock. wdt source selection. there are three types of selection: on-chip rc oscillator, instruction clock or disable the wdt. clrwdt times selection. this option defines how to clear the wdt by instruction. one time means that the clr wdt instruction can clear the wdt. two times means only if both of the clr wdt1 and clr wdt2 instructions have been executed, then wdt can be cleared. wake-up selection. this option defines the wake-up function activity. external i/o pins (pa only) all have the capability to wake-up the chip from a halt by a falling edge. (bit option) pull-high selection. this option is to decide whether a pull-high resistance is visible or not in the input mode of the i/o ports. pa, pb, pc, pd and pf are bit option. pfd selection. if pa3 is set as pfd output, there are two types of selections; one is pfd0 as the pfd output, the other is pfd1 as the pfd output. pfd0, pfd1 are the timer overflow signals of the timer/event counter 0, timer/event counter 1 re - spectively. pwm selection: (7+1) or (6+2) mode pd0: level output or pwm0 output pd1: level output or pwm1 output pd2: level output or pwm2 output pd3: level output or pwm3 output wdt time-out period selection. 2 12 /f s ~2 13 /f s ,2 13 /f s ~2 14 /f s ,2 14 /f s ~2 15 /f s ,2 15 /f s ~2 16 /f s . i 2 c bus function: enable or disable lvr selection. lvr has enable or disable options lvr voltage selection. 2.1v, 3.15v or 4.2v interrupt vector 04h trigger source selection. external interrupt or a/d interrupt application circuits note: 1. crystal/resonator system oscillators for crystal oscillators, c1 and c2 are only required for some crystal frequencies to ensure oscillation. for resonator applications c1 and c2 are normally required for oscillation to occur. for most applications it is not necessary to add r1. however if the lvr function is disabled, and if it is required to stop the oscillator when vdd falls below its operating range, it is recommended that r1 is added. the values of c1 and c2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. reset circuit the reset circuit resistance and capacitance values should be chosen to ensure that vdd is stable and re- mains within its operating voltage range before the res pin reaches a high level. ensure that the length of the wiring connected to the res pin is kept as short as possible, to avoid noise interference. 3. for applications where noise may interfere with the reset circuit and for details on the oscillator external com- ponents, refer to application note ha0075e for more information. HT46RU24 rev. 1.00 40 april 23, 2008 $ " % % 6 + = n n 3 1 + = $ , ' . . 3 + * 2 / + ' + / 3 ' 3 + 2 6 ' * . 1 ' 7 ' 3 ' " + ' ' 2 3 . 2 3 * + 2 * 3 2 + ' ( + 6 ' ( 6 + + d * + + = + d * $ % $ " % % * ) ? ) ? ) ) ) HT46RU24 rev. 1.00 41 april 23, 2008 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. HT46RU24 rev. 1.00 42 april 23, 2008 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z HT46RU24 rev. 1.00 43 april 23, 2008 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc + [m] + c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc + x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT46RU24 rev. 1.00 44 april 23, 2008 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT46RU24 rev. 1.00 45 april 23, 2008 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT46RU24 rev. 1.00 46 april 23, 2008 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m] + 1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT46RU24 rev. 1.00 47 april 23, 2008 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT46RU24 rev. 1.00 48 april 23, 2008 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT46RU24 rev. 1.00 49 april 23, 2008 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skipif[m]=0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skipifacc=0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT46RU24 rev. 1.00 50 april 23, 2008 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skipif[m]=0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skipifacc=0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT46RU24 rev. 1.00 51 april 23, 2008 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skipif[m]=0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT46RU24 rev. 1.00 52 april 23, 2008 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT46RU24 rev. 1.00 53 april 23, 2008 package information 28-pin skdip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 1375 1395 b 278 298 c 125 135 d 125 145 e16 20 f50 70 g 100 h 295 315 i 330 375 0 15 HT46RU24 rev. 1.00 54 april 23, 2008 ) ) 4 1 . / * % & 28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12 0 10 HT46RU24 rev. 1.00 55 april 23, 2008 4 1 . / * k % & 48-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 613 637 d85 99 e 25 f4 10 g25 35 h4 12 0 8 HT46RU24 rev. 1.00 56 april 23, 2008 . 4 1 . / * k % & product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 62 1.5 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 ssop 48w symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 100 0.1 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 32.2+0.3 0.2 t2 reel thickness 38.2 0.2 HT46RU24 rev. 1.00 57 april 23, 2008 / carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.1 b0 cavity width 18.34 0.1 k0 cavity depth 2.97 0.1 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 HT46RU24 rev. 1.00 58 april 23, 2008 ( + * + / + + ssop 48w symbol description dimensions in mm w carrier tape width 32.0 0.3 p cavity pitch 16.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 14.2 0.1 d perforation diameter 2.0 min. d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 12.0 0.1 b0 cavity width 16.20 0.1 k1 cavity depth 2.4 0.1 k2 cavity depth 3.2 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 25.5 HT46RU24 rev. 1.00 59 april 23, 2008 + * / + + ( HT46RU24 rev. 1.00 60 april 23, 2008 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, gaoxin m 2nd, middle zone of high-tech industrial park, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2008 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. |
Price & Availability of HT46RU24
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |